Guides
5 notes. Each one names its bench, its instruments and the validation runs that must pass before a setting is trusted.
Memory & Fabric
Subtiming work on DDR5, and the lane topology the rest of the platform hangs off.
| Note | Section | Read | Risk | Revised |
|---|---|---|---|---|
| DDR5 subtiming tuning on AM5 and LGA1700 Hand-tuning DDR5 subtimings, with the refresh window as the largest single lever | Memory & Fabric | 16 min | risk: moderate | 2026-08-28 |
| PCIe lane topology, bifurcation and link verification Splitting a x16 root port and proving on Linux that every link trained as intended | Memory & Fabric | 16 min | risk: low | 2026-08-28 |
Power & Thermals
What the regulator actually delivers under load, and how the voltage/frequency curve is shaped.
| Note | Section | Read | Risk | Revised |
|---|---|---|---|---|
| VRM load line, droop and thermal analysis What the phase count buys, what LLC costs, and how to measure a rail software cannot see | Power & Thermals | 16 min | risk: moderate | 2026-08-28 |
| Per-core Curve Optimizer: finding each core's voltage floor Per-core CO counts found by bisection, validated at idle rather than under load | Power & Thermals | 16 min | risk: moderate | 2026-08-28 |
Firmware
Reading, altering and recovering the image the board boots from.
| Note | Section | Read | Risk | Revised |
|---|---|---|---|---|
| UEFI firmware inspection, modification and recovery Read the SPI chip, write one region back, and recover a board that will not POST | Firmware | 16 min | risk: can brick | 2026-08-28 |